For years, the race in AI infrastructure centred on one question: who had the most powerful chips? That era is ending. As generative AI models scale rapidly, the primary data-centre bottleneck is shifting from transistor performance to interconnect bandwidth and latency. The challenge is no longer inside the chip — it is between chips.

As AI clusters scale toward multi-hundred-thousand GPU configurations, three constraints are emerging simultaneously: rack-level power is surging toward hundreds of kilowatts; higher data rates pushing electrical interconnects to their physical limits; and interconnect architecture becoming a system-level challenge involving packaging, cooling, and power delivery in unison. The industry conversation has decisively shifted from "faster chips" to "faster, smarter systems."

Nothing illustrates the new reality more starkly than the power problem. Vittorio Pierangeli of Rolls-Royce Power Systems, speaking at Data Centre LIVE 2026 in London, was direct: "Power is the main bottleneck today for the realisation of data centre infrastructure." He noted that lead times to secure grid connections are now running to five to seven years in several global jurisdictions.

Traditional utility planning was designed for gradual, predictable growth — a new manufacturing plant adding 20–30MW over several years. Data centres serving AI workloads shatter this model by demanding hundreds of megawatts with deployment timelines measured in months. The mismatch is acute. "Now the wait for many data centres is potentially up to five to ten years to deliver the energy they need directly from the grid," industry experts have warned. In the AI race, five to ten years might as well be forever.

The response has been a dramatic shift toward on-site generation strategies — once unthinkable, now a necessity — as operators bypass grid bottlenecks to keep pace with soaring AI-driven demand. Grid connection requests linked to data centres have surged dramatically, accelerating this transition.

Inside the facility, the bottleneck has migrated to connectivity. At 200 Gb/s per lane and beyond, copper's physics becomes the limiting factor — traditional passive copper can no longer span beyond a single server rack and sometimes struggles even within one. This is driving a structural transition: optics must move closer to the compute and switching silicon to reduce loss, power consumption, and reach constraints.

The industry is moving fast. 800G deployments are accelerating sharply through 2026, while 1.6T optical connectivity is beginning to transition from roadmap planning into real-world deployment. Future roadmaps already point toward 3.2 Tb/s per fibre in next-generation AI systems. The datacom optical component market is forecast to exceed $16 billion in 2025, with some optical and semiconductor segments already registering 40–65% year-over-year growth driven entirely by AI infrastructure demand.

Co-Packaged Optics (CPO) is widely regarded as the long-term solution for AI scale-up architectures, integrating optical components directly with switching silicon to slash power and latency. In parallel, AI back-end networks are driving dense east-west traffic patterns that are accelerating front-end network upgrades from 25G to 100G and higher — with operators racing to avoid the new bottlenecks before they bite.

Power density is reshaping the physical design of facilities. As racks push toward hundreds of kilowatts, liquid cooling is transitioning from a niche option to a mainstream requirement — with rear-door chillers and liquid-to-chip solutions becoming standard. AI chips generate unprecedented heat loads, and water scarcity has evolved from an operational footnote to a primary consideration in site selection.

Meanwhile, a structural shift in AI workloads is adding urgency. Training is intensive but episodic; inference is repetitive and ubiquitous. A growing body of evidence suggests inference already accounts for the majority of computing effort associated with deployed AI systems. Bandwidth limitations — both within and between chips — are emerging as the next major performance bottleneck specifically because inference at scale places sustained, relentless pressure on memory bandwidth and interconnect efficiency.

As AI clusters outgrow the boundaries of a single site, a new concept is taking hold: scale-across architecture, where workloads span multiple locations stitched together by high-speed optical fabric. The future is not "all edge" or "all hyperscale" — it is a hybrid model where latency-critical inference moves outward while frontier training stays concentrated at massive centralised campuses where power and networking economics are strongest.

Key Takeaways

• →The AI infrastructure bottleneck has shifted decisively from compute performance to interconnect, power delivery, and data movement — fundamentally rewriting data centre design priorities.
• →Grid connection wait times have ballooned to five to ten years in many jurisdictions, forcing operators to pursue on-site generation strategies as an urgent alternative.
• →Copper interconnects are hitting physical limits at 200 Gb/s per lane, accelerating the structural transition to optical connectivity — with 800G mainstream and 1.6T entering real deployment in 2026.
• →Inference workloads — repetitive, ubiquitous, and growing rapidly — are becoming the dominant AI compute story, placing sustained pressure on memory bandwidth and interconnect efficiency.
• →Liquid cooling has moved from niche to necessity as rack power densities escalate, with liquid-to-chip solutions and rear-door chillers becoming standard infrastructure for AI-dense facilities.
• →The winner of the data centre race will not be whoever builds biggest, but whoever best masters power access, optical bandwidth, cooling strategy, and vertical integration across the full infrastructure stack.